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VOYAGES FOR THE MUSCOVY COMPANY

The Letter of Master George Killingworth, the Company’s First Agent in Muscovy

The Discovery of Muscovy by Richard Hakluyt is part of the HackerNoon Books Series. You can jump to any chapter in this book here . The Copy of the Duke of Muscovy and Emperor or Russia his Letters, sent to King Edward VI., by the hands of Richard Chanceler. The Copy of the Duke of Muscovy and Emperor or Russia his Letters, sent to King Edward VI., by the hands of Richard Chanceler. “The almighty power of God, and the incomprehensible Holy Trinity, rightful Christian belief, etc.  We, great Duke Ivan Vasilivich, by the grace of God Emperor of all Russia, and great Duke of Vladermerskij, Moskowskij, Novogrodskij, Cazanskii, Pskanskii, Smolenskii, Tuerskij, Hugorskij, Permskii, Veatskii, Bolgarskii, with divers other lands, Emperor also and great Duke of Novogoroda, and in the low countries of Chernigouskii, Rezanskii, Volotskii, Refskii, Belskii, Rostouskii, Yaroslavskii; Belocherskii, Oodorskii, Obdorskii, Codinskii, and many other countries, lord over all the north coast, greeting. “Before all right great and worthy of honour Edward, King of England, &c., according to our most hearty and good zeal, with good intent and friendly desire, and according to our holy Christian Faith and great governance, and being in the light of great understanding, our answer by this our honourable writing unto your kingly governance, at the request of your faithful servant Richard Chanceler, with his company, as they shall let you wisely know, is thus.  In the strength of the twentieth year of our governance, be it known, that at our sea coasts arrived a ship, with one Richard and his company, and said, that he was desirous to come into our dominions, and according to his request hath seen our Majesty and our eyes; and hath declared unto us your Majesty’s desire as that we should grant unto your subjects, to go and come, and in our dominions, and among our subjects to frequent free marts, with all sorts of merchandises, and upon the same to have wares for their return.  And they have also delivered us your letters which declare the same request.  And hereupon we have given order, that wheresoever your faithful servant Hugh Willoughbie land or touch in our dominions, to be well entertained, who as yet is not arrived, as your servant Richard can declare. “And we, with Christian belief and faithfulness, and according to your honourable request and my honourable commandment will not leave it undone, and are furthermore willing that you send unto us your ships and vessels, when, and as often as they may have passage, with good assurance on our part to see them harmless.  And if you send one of your Majesty’s council to treat with us, whereby your country merchants may with all kinds of wares, and where they will, make their market in our dominions, they shall have their free mart with all free liberties through my whole dominions with all kinds of wares, to come and go at their pleasure, without any let, damage, or impediment, according to this our letter, our word, and our seal, which we have commanded to be under-sealed.  Written in our dominion in our town and in our palace in the Castle of Moscow, in the year seven thousand and sixty, the second month of February.” This letter was written in the Muscovian tongue, in letters much like to the Greek letters, very fair written on paper with a broad seal hanging at the same, sealed in paper upon wax.  This seal was much like the broad seal of England, having on the one side the image of a man on horseback in complete harness fighting with a dragon. Under this letter was another paper written in the Dutch tongue, which was the interpretation of the other written in the Muscovian letters.  These letters were sent the next year after the date of King Edward’s letters, 1554. About HackerNoon Book Series: We bring you the most important technical, scientific, and insightful public domain books. This book is part of the public domain. Richard Hakluyt (2003). The Discovery of Muscovy. Urbana, Illinois: Project Gutenberg. Retrieved October 2022 https://www.gutenberg.org/cache/epub/4076/pg4076-images.html This eBook is for the use of anyone anywhere at no cost and with almost no restrictions whatsoever. You may copy it, give it away or re-use it under the terms of the Project Gutenberg License included with this eBook or online at www.gutenberg.org , located at https://www.gutenberg.org/policy/license.html .

The Copy of the Duke of Muscovy and Emperor or Russia his Letters, sent to King Edward VI.

THE NEW NAVIGATION AND DISCOVERY OF THE KINGDOM OF MUSCOVY

The Discovery of Muscovy by Richard Hakluyt, is part of the HackerNoon Books Series. Read this book online for free on HackerNoon! : The Discovery of Muscovy Title : Richard Hakluyt Author : May 1, 2003 [EBook #4076] Most recently updated: September 27, 2014 Release date : English Language Table of Links INTRODUCTION The New navigation and discovery of the Kingdom of Muscovy The Copy of the Duke of Muscovy and Emperor or Russia his Letters, sent to King Edward VI., by the hands of Richard Chanceler. The Coins, Weights, and Measures, used in Russia. The Letter of Master George Killingworth, the Company’s First Agent in Muscovy, A Discourse The Voyage The Voyages of Ohthere and Wulfstan Elegiac verse by William Wordsworth About HackerNoon Book Series: We bring you the most important technical, scientific, and insightful public domain books. This book is part of the public domain. Richard Hakluyt (2003). The Discovery of Muscovy. Urbana, Illinois: Project Gutenberg. Retrieved October 2022 https://www.gutenberg.org/cache/epub/4076/pg4076-images.html This eBook is for the use of anyone anywhere at no cost and with almost no restrictions whatsoever. You may copy it, give it away or re-use it under the terms of the Project Gutenberg License included with this eBook or online at www.gutenberg.org , located at https://www.gutenberg.org/policy/license.html .

The Discovery of Muscovy by Richard Hakluyt - Table of Links

Metamorphosis Commenced: Network States v0.01

মেটামরফোসিস শুরু হয়েছে: নেটওয়ার্ক স্টেটস v0.01

Beginn der Metamorphose: Netzwerkzustände v0.01

Metamorfosis comenzada: Estados de la red v0.01

La métamorphose a commencé : États du réseau v0.01

मेटामोर्फोसिस शुरू हुआ: नेटवर्क स्टेट्स v0.01

変態開始: ネットワーク状態 v0.01

변형 시작됨: 네트워크 상태 v0.01

Metamorfose iniciada: Estados de rede v0.01

Метаморфоза началась: Состояния сети v0.01

Metamorfoz Başladı: Ağ Durumları v0.01

Bắt đầu biến thái: Trạng thái mạng v0.01

蜕变开始：网络状态 v0.01

581 Stories To Learn About Non Fiction

There’s no denying the fact that the performance of our code carries a lot of importance. For countless applications, including HPC simulations, gaming, graphics, etc., performance does not just mean faster execution and less waiting times. It also directly relates to cost, energy usage, and user experience. A better-performing code often saves a lot of computational resources, potentially leading to cost-cutting measures, especially when running in supercomputing and data centers. However, the journey to improve performance can be a formidable challenge, with complexities that demand a strategic approach. Before enhancing performance, a crucial first step is to gauge the theoretical limits of achievable performance. This ensures the programmer knows what he’s aiming for and how far he can go with the performance optimization. This is where the performance models like the roofline model emerge as a guiding beacon. By providing insights into the theoretical performance limits and pinpointing bottlenecks, the roofline model becomes an invaluable tool for computational excellence, allowing developers to make informed decisions on performance optimization strategies. In this story, I’ll dig deeper into what the roofline model is all about. We’ll also go through a detailed example to showcase how to identify whether our algorithm is compute or memory-bound. The roofline model allows us to determine if our algorithm runs at its peak potential or requires more improvement. The rooflines The theoretical limits (or the rooflines) come mainly from the machine's architecture and memory characteristics. As discussed earlier in my blog post on the , it is up to the programmer to exploit the hardware’s capability for the maximal performance of the algorithm. necessity of parallelism Two major upper limits (or rooflines) for the achievable performance are: Peak performance Memory throughput/bandwidth Peak performance [operations/s] Applicable peak performance is dependent on the computational resources available on the hardware. Different architectural factors affect that, such as the processor’s clock frequency and pipelining implementation. This roofline also depends on the kinds of operations our code performs. For instance, the rooflines may differ for one code with fused multiply-add (FMA) operations and another with basic arithmetic operations. The capability of the algorithm to use vectorization or SIMD will also change its performance. Memory throughput/bandwidth Another ceiling comes from the fact that only a limited amount of data can be transferred between the memory and the CPU. This roofline is dependent on two aspects: the code-dependent computational (or arithmetic or operational) intensity [operations/byte] and the hardware-dependent peak bandwidth [byte/s]. What is computational intensity? Computational intensity determines the number of bytes transferred between the memory and the CPU for every floating-point operation in the algorithm. Put simply, it is the ratio of the total number of floating-point operations in your algorithm to the number of bytes transferred. Thus, measured as . operations/byte What about the peak memory bandwidth? Modern-day computers have an intricate memory hierarchy. A high-level representation of the memory hierarchy is as shown below: There are several data cache levels (mostly L1 to L3), followed by DRAM. The memory bandwidth of each of these memories varies considerably. While the Level 1 cache (L1) has the highest memory bandwidth, DRAM has the lowest. However, the capacity of L1 is substantially low (mainly in the orders of KBs in modern personal computer processors). In contrast, DRAM can be significantly larger (in the order of several GBs). A set of benchmarks like the can be used to identify the peak memory bandwidth. STREAM benchmark The Naïve roofline model Having discussed the basics, let’s proceed to how we utilize all this information to estimate our peak performance. A simple roofline model (the so-called Naïve roofline model) can be represented as: : upper bound on the performance [operations/s] Pₘₐₓ Machine dependent parameters: : applicable peak performance [operations/s] Pₚₑₐₖ : applicable peak bandwidth [byte/s] bₘₐₓ Code dependent parameter: : computational intensity [operations/byte] I As discussed above, the bottleneck can be the execution of work ( ) or the data path ( ). Pₚₑₐₖ I*bₘₐₓ Assumptions behind the model Several vital considerations contribute to the simplicity and effectiveness of the roofline model. First and foremost, the model assumes an ideal scenario where data transfer and core execution are perfectly overlapped, emphasizing the importance of seamless coordination between these two aspects of computation. The model operates on the principle that the slowest limiting factor, whether core execution or data transfer, dictates overall performance. In this competition, the “winner” is the factor with the most significant impact, while others are presumed to have negligible effects. Notably, latency effects are disregarded, implying an assumption of a perfect streaming mode where data transfer is already in progress. Finally, the model focuses on “steady-state” code execution, excluding wind-up and wind-down effects and assuming an entire pipeline, adding to its simplicity. Despite its simplicity, the roofline model proves highly effective by encapsulating this complexity, offering a practical tool for communication between High-Performance Computing (HPC) experts and application scientists. Refined roofline model The Naïve roofline model can be refined and improved in many ways. For starters, adding multiple rooflines for different kinds of arithmetic operations can improve the roofline model. Similarly, using different memory bandwidths for various available memories makes the model more expressive. An example is shown below: While doing theoretical calculations (as we’ll do very soon), the Naïve roofline model neglects latency effects. However, if we have sufficient information, we can include latency effects in our calculations, improving our predictions. Roofline model in action Let’s use what we learned above to apply the roofline model to a real problem. This example is inspired by my learnings while studying one of my favorite courses at the Technical University of Munich: Advanced Programming by the . TUM SCCS My machine has a single-core CPU with 2GHz frequency (pretty oldish, right?) and the following specifications: This CPU can perform 4 double-precision (8 bytes) floating point operations simultaneously (i.e., it is vectorized). 2. The latency of basic arithmetic operations (+, -, *) is 2 cycles (one operation per two cycles). 3. The latency of the fused multiply add operation (a += b * c) is 3 cycles. 4. These operations are not pipelined. 5. This CPU has 2 load units and 1 store unit, and each unit can accommodate 32 bytes (4 doubles). 6. Accessing the cache memory is pipelined and costs 5 cycles. The cache operates at 2 GHz. 7. Accessing the main memory is not pipelined and costs 10 cycles. The main memory operates at 800 MHz. 8. Both types of memory can either load 2 vector registers (2 × 32 bytes) or store 1 vector register (32 bytes) simultaneously. 9. Assume that one load/store unit of the CPU can load/store one vector register. Given all the architectural specifications, we can first calculate the hardware-dependent parameters of our model. After doing so, we can look at our code and proceed with the calculations of computational intensity. Calculating the applicable peak performance The theoretical peak performance will depend on the kind of operations we are doing. For basic arithmetic operations: As the CPU can perform 4 double-precision floating point operations simultaneously and the latency of basic arithmetic operations is 2 cycles, the theoretical peak performance can be measured as: For fused-multiplication-addition (FMA) operations: For FMA operations, there would be 2 FLOP/item (addition + multiplication). The latency, however, is 3 cycles. Thus, the theoretical peak performance is: Calculating the memory bandwidth Unfortunately, calculating the applicable memory bandwidth is a bit more complicated. As discussed above, different types of memories can have different bandwidth values (depending on their size and proximity to the processor). So, to accurately model the rooflines, it is essential to consider as many of these as possible. For our example, we’ll focus on the cache and main memory. Theoretical read bandwidth of the memory: Neglecting the latency effects due to the connection with the CPU, the read bandwidth of the main memory and cache will depend on their capacity and clock frequency. Both kinds of memory can either load 2 vector registers (2 × 32 bytes) or store 1 vector register (32 bytes) simultaneously (8th specification above). For main memory (without latency effects): For Cache (without latency effects): Similar calculations can be done for the theoretical write bandwidth. Applicable read/write bandwidth of the memory: In any real case scenario, the connection between the CPU and the memory (both cache and main memory) will bring in some latency effects. Because of these effects, the CPU can use only a fraction of the available bandwidth. So, it is essential to consider these effects. For main memory read (with latency effects): For main memory write (with latency effects): As mentioned in the specifications, access to the cache memory is (6th specification above). If the pipeline is full, the latency effects can be ignored for our calculations. pipelined For cache read (with pipelined access): For cache write (with pipelined access): Calculating the computational intensity Let’s consider an application whose core computation involves a matrix-matrix multiplication function. Here, the inner-most loop over computes the element of matrix by taking the dot product of the -th row of with the -th column of . i (row,col) result row left col right Here is the complete code: // result[row,column] = dot_product(left[row, :], right[:, col])
void matrix_mult(size_t rows, size_t columns, size_t k,
             double *left, double *right, double *result) {
  for (auto row = 0; row < rows; ++row) {
   for (auto col = 0; col < columns; ++col) {
     for (auto i = 0; i < k; ++i) {
       if (i == 0) {
         result[row*columns + col] = left[row*k + i] * right[i*columns + col];
       }  
       else {
         result[row*columns + col] += left[row*k + i] * ri[i*columns + col];
       }
    }
  }
 }
} As discussed above, Computational intensity determines the number of bytes transferred between the memory and the CPU for every floating-point operation in the algorithm. Put simply, it is the ratio of total number of floating-point operations in your algorithm to the number of bytes transferred. Thus, measured as . operations/byte Let’s start with the number of floating-point operations. Total number of floating-point operations: In total, the loops run for iterations. rows*columns*k However, for all , only multiplications are performed. So, a total of multiplications are performed. i = 0 rows*columns For the remaining iterations (that go inside the part), FMA (fused-multiply-add) operations are performed. In total, there are FMA operations. Each FMA operation consists of 2 floating-point operations. Thus, we have: else (k-1) *rows*columns Total multiplications: rows*columns Total FMA operations: (k-1)*rows*columns Total floating-point operations: … (i) (2k-2)*rows*columns + rows*columns = (2k-1)*rows*columns Total memory transactions: The next step is identifying the number of bytes transferred between the memory and the processor. This can be calculated by determining the total number of memory transactions between the two. Note: For simplification, we’ll assume that does not require memory interaction for the intermediate result . (a += b * c) b * c The algorithm comprises several read-and-write operations over the matrices. To calculate the total number of transactions, we need to consider all these (and potentially more). left, right, and result Let’s begin! matrix is read in every iteration. So, the total reads of the matrix sum up to . left left rows*columns*k Similarly, the matrix is also read these many times. right Is that all? No. The matrix is also read for FMA operations ( ). The total reads amount to . result _a =_ **_a_** _+ b * c_ rows*columns*(k-1) Finally, the matrix is accessed a total of times for writing operations. result rows*columns*k To summarize: Total read operations: … (j) 2*rows*columns*k + rows*columns*(k-1) = rows*columns*(3k-1) Total write operations: … (k) rows*columns*k Thus, the computational intensity can be calculated as: For reading data: Using and (i) (j): For writing data: Using and (i) (k): Putting it all together Phew! We’re almost there. Having calculated all the elements of our roofline model, let’s put everything together and see how our algorithm is performing and what the limiting component of the system is. Again, we break down everything in two cases. When the cache is not involved The reading speed can be calculated using the computational intensity calculated in and the applicable read bandwidth for the main memory in (l) (e): Similarly, the writing speed can be calculated using the computational intensity calculated in and the applicable write bandwidth for the main memory in (m) (f): Since most of the computations in the innermost loop use the fused-multiply-add instruction, we will take the FMA-peak as the peak floating-point performance of our CPU for both cases. Thus, using , the peak performance of our algorithm can be predicted as: (b) Looking at these numbers, it can be clearly seen that our algorithm is memory bound. It can do more floating-point operations, but our processor is not able to read/write the data fast enough. When the cache is involved The reading speed can be calculated using the computational intensity calculated in and the applicable read bandwidth for the cache in (l) (g): Similarly, the writing speed can be calculated using the computational intensity calculated in and the applicable write bandwidth for the cache in (m) (h): Again, using , the peak performance of our algorithm can be predicted as: (b) In this case, the algorithm is compute bound. While it can access the data quickly, it doesn’t have enough resources to perform as many floating-point operations. Thus, maybe we should consider a faster CPU for our algorithm! Final words This is how our roofline model would look like: This graph clearly lays out what the theoretical limits of our algorithm could be. Being aware of them, we can carefully identify the potential bottlenecks of our algorithm and try to reach the theoretical limits. Similarly, this also helps us identify when to stop optimizing our code, as maybe our hardware won’t allow further optimizations. As modern-day processors become more powerful, many algorithms tend to be memory-bound (because of the so-called “ ”). This is the reason why developers invest so much effort in improving the memory-access patterns. Memory Wall It is important to mention here that roofline analysis doesn’t always involve a lot of hand calculations. There are a range of open-source and commercial tools that may help us create powerful roofline visualization. These tools include — for collecting hardware specifiic roofline ceilings and tools like , and for collecting application specific performance. Empirical Roofline Tool (ERT) LIKWID Intel® Advisor Roofline Intel® VTune™ I hope this story helped you understand the basics and complexities of the roofline model! Suggested resources [1] A very short intro to the Roofline model — YouTube [2] Roofline_MuCoSim-SS22.pdf (fau.de) [3] Performance model — HPC Wiki (hpc-wiki.info) [4] RooflineVyNoYellow.pdf (berkeley.edu) [5] Roofline model (cornell.edu) [6] Tutorial-ISC2019-Intro-v2.pdf (nersc.gov) [7] Chair of Scientific Computing (tum.de) [8] berkeleylab / cs-roofline-toolkit — Bitbucket Also published . here Featured Photo by on Joshua Hoehne Unsplash

Understanding the Roofline Model 

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