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In the previous set of articles we have worked our way through configuring a vCPU and getting it to run in 32bit mode with paging enabled. In this article we will take it a step further and enable 64bit mode. Before we can run a CPU in 64bit mode we need to "reconfigure" our page tables. Don't worry - this exercise should be a walk in a park compared to the previous one (enabling paging and switching CPU to 32bit mode). 64bit vs 32bit page tables Before we dive into implementation lets have a look how is paging different in 64bit mode to the one used in 32bit mode[1]. In 32bit mode we used three level paging scheme. The tables were called 1. Page Directory Table (PDT) 2. Page Directory (PD) 3. Page Table (PT) We used one part of virtual address (VA) in combination with CR3 to locate an entry in PDT called PDTE. Then we used PDTE in combination with another part of VA to locate an entry in PD (PDE). From there we went on and used yet another part of VA in combination with PDE to locate an entry in PT (PTE). And finally we combined PTE with VA to come up with physical address (PA). In summary, we traversed table structures in this order: . PDT -> PD -> PT -> PA (Physical Address) In 64bit mode x86 uses 4 level paging scheme in which tables have the following names: 1. PML4 (Page Map Level 4 Table) 2. PDP (Page Directory Pointer) 3. PD (Page Directory) 4. PT (Page Table) In this scheme tables are traversed in order . PML4 -> PDP -> PD -> PT Also keep in mind that in long mode page table contains 8 byte entries compared to 4 byte entries in 32 bit mode. That means each of the tables can be up to 2^9 * 2^3 = 4096 (or 0x1000) bytes large The following image from Intel System Programming Guide best illustrates the process. that works through an example where 0xc000 is identity mapped. Here you can find an illustration Create page tables Firstly, let's change our page tables. Instead of using uint32_t byte which is 4 bytes in size we will use uint64_t. In this example we have 0x10000 (65536) bytes that are allocated for the VM. We will identity map these area. The addresses that will be used for tables are 0x1000, 0x2000, 0x3000 and 0x4000 for PML4, PDP, PD and PT respectively. First three tables will have only one page that points to the following one. That means that PML4 will have one entry pointing to PDP. PDP will have one entry pointing to PD. PD will have one entry pointing to PT. Reason is that each of these tables can address up to 2^9 = 512 entries. This means we need only one PT which will host our 16 entries (0x10000 / 0x1000 = 0x10 = 16). { pml4e = | ; (mem, &pml4e, ); pdpte = | ; (mem + , &pdpte, ); pde = | ; (mem + , &pde, ); pte_1 = | ; (mem + , &pte_1, ); pte_2 = | ; (mem + , &pte_2, ); pte_3 = | ; (mem + , &pte_3, ); pte_4 = | ; (mem + , &pte_4, ); pte_5 = | ; (mem + , &pte_5, ); pte_6 = | ; (mem + , &pte_6, ); pte_7 = | ; (mem + , &pte_7, ); pte_8 = | ; (mem + , &pte_8, ); pte_9 = | ; (mem + , &pte_9, ); pte_10 = | ; (mem + , &pte_10, ); pte_11 = | ; (mem + , &pte_11, ); pte_12 = | ; (mem + , &pte_12, ); pte_13 = | ; (mem + , &pte_13, ); pte_14 = | ; (mem + , &pte_14, ); pte_15 = | ; (mem + , &pte_15, ); pte_16 = | ; (mem + , &pte_16, );
} void createPageTable ( *mem) void uint64_t 0x2000 0x3 memcpy 8 uint64_t 0x3000 0x3 memcpy 0x1000 8 uint64_t 0x4000 0x3 memcpy 0x2000 8 uint64_t 0x0000 0x3 memcpy 0x3000 8 uint64_t 0x1000 0x3 memcpy 0x3008 8 uint64_t 0x2000 0x3 memcpy 0x3010 8 uint64_t 0x3000 0x3 memcpy 0x3018 8 uint64_t 0x4000 0x3 memcpy 0x3020 8 uint64_t 0x5000 0x3 memcpy 0x3028 8 uint64_t 0x6000 0x3 memcpy 0x3030 8 uint64_t 0x7000 0x3 memcpy 0x3038 8 uint64_t 0x8000 0x3 memcpy 0x3040 8 uint64_t 0x9000 0x3 memcpy 0x3048 8 uint64_t 0xa000 0x3 memcpy 0x3050 8 uint64_t 0xb000 0x3 memcpy 0x3058 8 uint64_t 0xc000 0x3 memcpy 0x3060 8 uint64_t 0xd000 0x3 memcpy 0x3068 8 uint64_t 0xe000 0x3 memcpy 0x3070 8 uint64_t 0xf000 0x3 memcpy 0x3078 8 The above code is not the most efficient way to do memory mapping. Normally you would populate tables using loops but because goals of these examples is teaching the code is left verbose on purpose. Enable long mode To enable long mode we need to do three more things. 1. Set PAE bit in CR4 2. Set LMA bit in EFER register. 3. Set L bit in CS To set those registers we will read special registers using KVM_GET_SREGS ioctl. Setting PAE bit is straightforward. We read current value and xor it with 0x20 (bit 5 set to 1). sregs.cr4 = sregs.cr4 | ; 0x20 Setting LMA bit in EFER comes with a caveat. Most documentation will tell you that need to set bit 9 in EFER register to enable long mode. That is true when working with bare metal (no VM). For a VM to enter long mode you need to set bit 9 and 11. To understand why take a look at description of EFER register in "Intel 64 and IA-32 Architectures Software Developer’s Manual Volume 4: Model-Specific Registers". You can see that when 11th bit is set it tells CPU that long mode (IA-32e) is enabled. When working with a CPU you can enable long mode but then you should check if CPU really enabled it. When working with VM setting bit 9 without setting bit 11 will not even work. Now we can use the same technique that we used with CR4 register. This time we will be xor-ing with value 0x500 (bit 9 and 11 set). sregs.efer = sregs.efer | ; 0x500 Lastly we need to set L bit in CS (code segment) register. It is sometimes misunderstood how code segments are used in IA-32e mode. Specifically it's often thought that they don't exist or are not used. Truth is that some fields are ignored (e.g. base address and limit fields), some are treated as 0 in some calculations and the remaining bits are used normally. Code segment descriptors and selectors are needed in IA-32e mode to and execution privilege level. establish processors operating mode What is relevant in our case is that setting bit L of the CS register and having IA-32e mode active means that processor starts using default address size of 64 bits and default operand size of 32 bits[R2]. In case we do not set this bit out processor will operate in 64 bit compatibility mode. sregs.cs.l = ; 0x1 And that's it. Now our VM is able to run 64 bit programs. Run program Finally, we need to compile a program that we can run. In my previous article I've spoken about differences between 16/32/64 bit programs and how to compile for each architecture. Let's use two toy programs in this example too. The first program will take two numbers in registers rax and rbx, compare them and output either N or Y depending whether the numbers are equal or not. From there it will jump to a different program (b.asm) that is located at memory address 0xc000. That program will output E (for end) and halt the machine. , , , , , .equal , , , , , , , , , , , ;a.asm BITS 64 mov rax 0x100000000 mov rbx 0x200000000 add rax rbx mov rbx 0x200000000 cmp rax rbx jz mov rax 'N' mov edx 0x3f8 out dx al mov rax 0xc000 jmp rax .equal: mov rax 'Y' mov edx 0x3f8 out dx al mov rax 0xc000 jmp rax ;b.asm BITS 64 mov rax 'E' mov edx 0x3f8 out dx al hlt Each of the programs can be compiled using : nasm nasm -O0 -o a.bin a.asm
nasm -O0 -o b.bin b.asm The tells to not use any optimizations. This is to ensure that we run 64 bit instructions rather than potentially optimizing out some instructions and using the same ones as in 32 bit mode. During normal operation you would let compiler optimize the code but in this case we want to be sure the code that we run is 64 bit and that vCPU is running in true long mode (IA32e / 64 bit mode). -O0 nasm Finally, if we run our program we will be presented with the following output: Conclusion This brings us to the end of yet another challenge. Our VM can now run 64 bit programs. You can already use it to run a lot of useful programs. To make it even more useful, in the next article we will look into exception handling. Stay tuned! Notes: 1. Technically there is one more variation of paging in 32bit mode in addition to the one we used in previous article. You can check out chapter on paging from Intel x86 manual [R1] References: [R1] Intel 64 and IA-32 Architectures Software Developer’s Manual Volume 3 (3A, 3B, 3C & 3D): System Programming Guide [R2] Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3 (3A, 3B, 3C & 3D): System Programming Guide - 5.2.1 Code-Segment Descriptor in 64-bit Mode

How to Enable 64bit Mode on x86

So far we have seen how to start up a VM, emulate CUPID instruction, run arbitrary and learned about segmentation and paging in a CPU. This already allows us to do a lot of useful things with our VM. However, our CPU is in so called real mode. In this article we will go through setting up paging structure and enabling . code protected mode with paging When protected mode is switched on, CPU will remain in segmentation mode. This segmentation in protected mode is not the same as segmentation in (checkout my previous article to learn more about this -> ). Segmentation is not used a lot today and long mode uses paging exclusively. real mode https://hackernoon.com/segmentation-and-paging-in-x86-xts3yp1 In this article we will do the following: Configure for paging CPU Load bootstrap program (program A) at memory location 0x4000 Load another program (program B) at memory location which will be mapped to virtual address 0x6000 0xc000 Switch CPU to protected mode with paging enabled starting execution in program A and doing a jump to 0xc000 Even though program B resides at physical address we expect it to be correctly executed when we execute a jump to from the first program due to paging that will be set up. 0x6000 0xc000 1. Configure CPU for paging Before CPU can start using paging we need to set up what is called page tables. In this exercise we will set up a 2 level page table. In my opinion this is the simplest to set up when starting. After going through this process (and reading a bit of ) I hope that you will be able to set up 3, 4 or even 5 level page tables. Intel manual First level page table is known as and each entry in that table is known as . PD is 4Kb aligned*. page directory (PD) page directory entry (PDE) Address of is derived from value stored in register CR3[31:12]. Bits CR3[11:2] are filled bits LA[31:22] while the last two bits are set to zero. PD contains a pointer to . Elements of page table are called . 4Kb aligned page table is located at memory location specified by bits PDE[31:12]. Bits [11:2] are filled with bits LA[21:12] and the last two bits are set to zero (same as previous step). PDE page table (PT) page table entries (PTE) Each points to a . The physical address of that page frame is formed by using bits PTE[31:12] and filling bits [11:0] with zeros. PTE Page Frame Following figure depicts the process. Lower 12 bits in CR3, PDE and PTE are status bits which we can use to configure paging mechanism. 1.1. Game plan Following is the image that depicts page mapping that we will implement. On the left hand side are Logical/Virtual addresses while on the right hand size you can see page frames that represent physical memory. As you read the following sections feel free to refer to the map above to enrich your understanding. 1.1 Identity map a region of memory Firstly we will identity map a small region of memory [0x0000 - 0x5fff]. This region will be used to store our PD, PT, stack and some other CPU relevant stuff. Page tables will be stored in memory region ranging from [0x1000, 0x2fff]. This will ensure that we can access our page tables once we enable paging mode. Now we know that PD and PT each use 10 bits of the linear address (LA) to select an entry. Using that many bits we can select 2^10 entries. Given each entry is 4 bytes in size that means our PD and each of the PTs that we create will be 4kb in size. If we decide to place those sequentially in memory each of the tables will be 0x1000 (4kb) bytes apart. We also know that last 12 bits of LA are used to select specific byte ( ) in a page frame. That tells us that a single page frame can have 2^12 = 4096 bytes = 4kb = 0x1000 . physical address / PA Each of the PTEs covers 4096 bytes large region of memory. That means we will need three PTEs to cover region of memory from 0x0000 to 0x2fff. Going backwards we know that PDE can select one of 2^10 = 1024 entries in PD. Each of which is 4bytes in size (Because 10 bits of LA are combined to produce address of PTE and then last two bits are set to 0). Given we need to index only the first PTE from PT we need only one PDE. We will place our PD at memory location 0x1000 and PT at 0x2000. Our mapping so far looks like this: CR3 = 0x1000 [0x1000] = 0x2003 (at location 0x1000, which is our PD we have value 0x2000 which is location of our PT). This is our only PDE. [0x2000] = 0x0003 [0x2004] = 0x1003 [0x2008] = 0x2003 [0x200c] = 0x3003 [0x2010] = 0x4003 [0x2014] = 0x5003 Check the following section to understand why the last digit is 3. Hint - those come from status bits. 1.2 Map "program region" The next area that we will map is [0xc000, 0xefff] That is, three blocks of 4Kb in size - 0xc000, 0xd000 and 0xe000. The mapping will be as follows: 1. [0xc000, 0xcfff] -> [0x6000, 0x6fff] 1. [0xd000, 0xdfff] -> [0x7000, 0x7fff] 1. [0xe000, 0xefff] -> [0x8000, 0x8fff] 1. [0xf000, 0xffff] -> [0x9000, 0x9fff] This mapping is a bit trickier so I made the following digram to demonstrate how mapping from LA 0xc000 to PA 0x3000 works. From the image we can see that our PTEs should be as follows: [0x2030] = 0x6003 [0x2034] = 0x7003 [0x2038] = 0x8003 [0x203c] = 0x9003 As you can see in the figure, the last digit being 3 in PDE and PTEs is due to setting status bits 0 and 1. Setting those bits tells CPU that the the PTE (for PDE) and page frame (for PTE) are present, readable and writable. 2. Implementation Now that we know what the page tables should look like implementing this is easy: { pde = | ; (mem, &pde, ); pte_1 = | ; (mem + , &pte_1, ); pte_2 = | ; (mem + , &pte_2, ); pte_3 = | ; (mem + , &pte_3, ); pte_4 = | ; (mem + , &pte_4, ); pte_5 = | ; (mem + , &pte_5, ); pte_6 = | ; (mem + , &pte_6, ); pte_7 = | ; (mem + , &pte_7, ); pte_8 = | ; (mem + , &pte_8, ); pte_9 = | ; (mem + , &pte_9, ); pte_10 = | ; (mem + , &pte_10, ); ;
} * void createPageTable ( *mem) void uint32_t 0x2000 0x3 memcpy 4 uint32_t 0x0000 0x3 memcpy 0x1000 4 uint32_t 0x1000 0x3 memcpy 0x1004 4 uint32_t 0x2000 0x3 memcpy 0x1008 4 uint32_t 0x3000 0x3 memcpy 0x100c 4 uint32_t 0x4000 0x3 memcpy 0x1010 4 uint32_t 0x5000 0x3 memcpy 0x1014 4 uint32_t 0x6000 0x3 memcpy 0x1030 4 uint32_t 0x7000 0x3 memcpy 0x1034 4 uint32_t 0x8000 0x3 memcpy 0x1038 4 uint32_t 0x9000 0x3 memcpy 0x103c 4 return 0 Here we use type uint32_t as it's size is 4 bytes and it's unsigned.  The first PDE entry will be placed at the beginning of memory block passed into the function. PTEs will be placed into the same region but offset by 0x1000 bytes. In previous articles we have seen that host OS needs to allocate some memory for a VM. *mem = mmap( , , PROT_READ | PROT_WRITE, MAP_SHARED | MAP_ANONYMOUS, , ); void NULL 0x8000 -1 0 We will use our function to populate that block of memory with correct data structures: createPageTable createPageTable(mem); 3. Executable programs We will write two programs that we can use to test our mapping. The first program (a.asm) will output character 'A' and be loaded at memory address . This area of memory is identity mapped so physical and virtual addresses are the same. 0x4000 The other program ( ) is loaded at virtual memory address 0xc000 which is mapped to physical address 0x6000. . If we see output of the second program we can say that we set up paging correctly. b.asm We will use jump instruction in prog.a to jump to 0xc000 Here is our program: a.asm [ ] , , , , , BITS 32 mov ax 'A' add ax '0' mov dx 0x3f8 out dx al mov eax 0xc000 jmp eax And here is our program: b.asm [ ] , , , , BITS 32 mov ax 'B' add ax '0' mov dx 0x3f8 out dx al hlt We will use to compile both of the programs: nasm nasm -o a.bin a.asm
nasm -o b.bin b.asm If you are interested in looking at binary code that was generated you can use tools like . I hope I'll write a blog post at some point where I'll disassemble one of this (or similar programs) and go through the generated binary file. objdump 4. Loading binary files into memory Now that we have files generated, we will need to load them into memory. Here is one way to do this. First in order for us to know how much memory to allocate we need to find out size of our binaries. We can use host OS's facilities to do so. get_file_size( fd) { (fstat(fd, &s) < ) { ;
  } s.st_size;
} off_t int ; struct stat s if 0 return -1 return We will also need a function to copy those files into memory used by the VM: { temp[ ]; r = read(fd, &temp, ); total_bytes_copied = ; (r != ) { (buf + total_bytes_copied, temp, r);
		total_bytes_copied += r;
		r = read(fd, &temp, );
	} total_bytes_copied;
} int read_into_buffer ( fd, *buf) int uint8_t uint8_t 32 int 32 int 0 while 0 memcpy 32 return Next, let's open binary files: a_fd = open( , O_RDONLY); (a_fd == ) { ( ); ;
} b_fd = open( , O_RDONLY); (b_fd == ) { ( ); ;
    } int "a.bin" if -1 printf "Could not open a.bin.\n" return -1 int "b.bin" if -1 printf "Could not open b.bin.\n" return -1 And copy them into VM memory: bytes_copied = read_into_buffer(a_fd, mem + ); (bytes_copied != a_fs) { ( ); ;
}

bytes_copied = read_into_buffer(b_fd, mem + ); (bytes_copied != b_fs) { ( ); ;
} int 0x3000 if printf "Expected to copy as many bytes as there are in a.bin.\n" return -1 0x5000 if printf "Expected to copy as many bytes as there are in b.bin.\n" return -1 Notice how we have offset files a.bin and b.bin by 0x3000 and 0x5000 bytes respectively. Since this block of memory will be attached to the VM starting at address 0x1000, programs a.bin and b.bin will be found at addresses 0x4000 and 0x6000 from the perspective of VM. .slot = ,
    .guest_phys_addr = ,
    .memory_size = ,
    .userspace_addr = ( )mem,
};

ioctl(vmfd, KVM_SET_USER_MEMORY_REGION, &region); = { struct kvm_userspace_memory_region region 0 0x1000 0x8000 uint64_t 5. Running CPU in protected mode with paging enabled There are two more pieces of puzzle that we need to address: tell vCPU where to find page tables tell vCPU to start in protected mode with paging enabled. CPU looks in register CR3 for the address of page tables. This is a special register and its value can be retried and set using and ioctl pair of commands. KVM_GET_SREGS KVM_SET_SREGS Protected mode for a CPU is enabled by setting bit 0 in CR0 register while paging is enabled by setting bit 31 in the same register. struct kvm_sregs sregs;
ioctl(vcpufd, KVM_GET_SREGS, &sregs);

sregs.cr3 = ;
sregs.cr0 = sregs.cr0 | ;

ioctl(vcpufd, KVM_SET_SREGS, &sregs); 0x1000 0x80000001 6. Run VM Finally, set instruction pointer (IP/rip) to 0x4000 (location of a.bin program): .rip = ,
};
ret = ioctl(vcpufd, KVM_SET_REGS, &regs); = { struct kvm_regs regs 0x4000 And we are ready to kick off our VM: ...
ioctl(vcpufd, KVM_RUN, )
... NULL And hopefully you'll be greeted with the following output: Complete source code is available at GitLab: . Check out the README on how to run the code if you get stuck. https://gitlab.com/mvuksano/kvm-playground/-/tree/master/04-protected-mode-with-paging Conclusion And that's it! You reached the end of this article. I hope that by now you have better understanding of what it takes to configure CPU for what most engineers take for granted. In the upcoming articles I will talk more about compiling programs for different architectures (16/32/64) and configuring CPU to work in 64 bit mode. Stay tuned. assembly References: [1] Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3A: System Programming Guide, Part 1, Chapter 4 Paging Glossary: PD - Page Directory PDE - Page Directory Entry PT - Page Table PTE - Page Table Entry VA - Virtual Address LA - Logical Address PA - Physical address

Enabling Paging for a Virtual Machine

Over the past two years, I have spoken with technical folks, salespeople, and executives at more than 100 IoT-related companies, and I have learned two things: 1) IoT is huge, 2) almost everyone defines IoT differently. In this article, I share what I have learned about IoT platforms and one way to categorize and think about them. What Is an IoT Platform? IoT is much more expansive than what most of us think of as the traditional Internet. It is growing faster too. There are more devices, protocols, security concerns, RF frequencies, architectural components, services, data, and related products. IoT is massive and broad. As such, the term ‘IoT Platform’ is really too broad to be useful to most people. I outline an example IoT platform below, but, in some regards, the concept of an ‘IoT Platform’ is about as meaningful as an ‘Internet Platform’ circa 2004. In fact, IoT has a lot more moving parts. One of the most challenging parts of many IoT projects is managing the hardware devices. This primarily means safely provisioning, maintaining and updating sensors and edge devices. Accordingly, much of the IoT literature (and many new products and startups) is centered around the communication between cloud-based UIs, edge devices, and sensors — MQTT, security keys, OTA firmware updates, RF frequencies, et al. Consider the value chain chart below I created which shows where some common IoT technical components fall on their life cycles. Components on the lower left of this graph are changing so rapidly it is hard for IoT platforms to manage them consistently. One of the most important jobs for an IoT platform is to make it easy to provision, update, and manage lots of devices and to keep everything secure. As you will see, platforms have a long way to go in this regard and the reason lies in where these activities fall on their life cycles. Once the data makes it past the edge and into the cloud, however, IoT projects become more familiar (in theory; more about this in a minute). Data flows to an API endpoint and is stored in the cloud (typically). So a platform should help stream and load potentially massive amounts of data into a data store and facilitate the retrieval of this data. Since AI and machine learning can be important to IoT solutions, platforms should also implement algorithms wherever they are needed (edge, cloud, device, client). Finally, creating and managing dashboards or ‘Single Panes of Glass’ can be an important part of an IoT project. Platforms should help connect dashboards to data. There are many other components and activities too but those are some common ones. Who should buy an IoT Platform? It is still early for IoT platforms. For example, there are no Industrial IoT platforms in the yet. And according to , IoT platforms have just passed over the Peak of Inflated Expectations and are careening towards the Trough of Disillusionment. Gartner Magic Quadrant Gartner’s Hype Cycle for Emerging Technologies As bad as that sounds, now is actually the best time to select your IoT Platform if you are thinking strategically and want to gain a competitive advantage. Otherwise, it’s the worst time. Entering a highly fragmented and confusing market with inflated expectations and no strategy does not bode well. In other words, if you are an early adopter, proceed with care but don’t expect an IoT platform to do much on its own without a lot of time and effort. If you’re a laggard, by the time you’re reading this, you can just ask your to build your platform for you. Amazon Robot The IoT Platform Market The IoT market is complex and highly fragmented. However, the cloud market which has the most influence over the IoT value chain is not fragmented. The top 3 cloud service providers (CSPs) of the market by revenue run rate (CR3 is 0.792). This creates an interesting dynamic which I discuss later. comprise around 80% This market fragmentation means that the components and products that make up any particular IoT solution are highly sensitive to that project’s specific requirements. The best components available to build one system will likely vary widely from those available to build another. This will not always be true, but it is true today. As an example, below is a value-chain graph I did which includes the companies/products that are being considered for one large industrial IoT project. This graph is 10 months old and 30% of it is already outdated for the project. Companies/products considered for a large enterprise IoT project Types of IoT Platforms If we define an IoT Platform as then at this high level of abstraction, there are basically two platform categories: anything on which you can build and operate an IoT Solution, (BROAD) CSP IoT Platforms* (SPECIALIZED) Platforms built on top of CSPs** *CSP — Cloud Service Provider **most IoT platforms are built/focused on cloud infrastructure even when they have on-prem options; many IoT platforms claim to support multiple CSPs even when they have a partnership with one CSP (1) CSP IoT Platforms The three are Amazon, Microsoft, and IBM. These (3) providers comprise almost 80% of the market and have a $52 billion revenue run rate (Dec 2018). Each CSP offers its own IoT platform: largest cloud servicer providers & AWS IoT AWS IoT Core Microsoft Azure IoT IBM IoT Other notable CSPs — Oracle, Google, and Alibaba — also offer IoT platforms. (2) Specialized IoT Platforms built on CSPs Next, there are IoT Platforms that are built on top of CSP infrastructures. There are hundreds of these platforms and they are offered by large and small companies alike. Consider the following IoT platforms and the CSPs with which they have partnered: Industrial IoT Platforms: → Azure GE Predix → AWS, Azure Siemens Mindsphere Some other specialized IoT Platforms: → AWS C3 IoT → SAP Leonardo IoT AWS, Google, Azure → Cisco Kinetic Azure Smaller, specialized IoT Platforms: → Azure Mariner Datonis→ AWS, Azure Altizon CSP IoT Platforms vs. Specialized IoT Platforms CSP IoT Platforms offer a broad and highly flexible set of services and components which can be used to build almost any IoT solution. If you have the time, budget and resources, CSP platforms offer the basic building blocks. Specialized IoT platforms are supposed to accelerate time-to-market and serve as outsourced expertise in verticals and specific applications. The smaller, specialized IoT platform companies tend to operate in a few verticals and are focused on products whereas the larger, specialized IoT platforms, such as GE Predix and Siemens Mindsphere, offer market-level platforms geared towards entire industries, such as Industrial IoT Platforms. , CSP IoT platforms would offer small Lego bricks If platforms were Legos CSP IoT Platforms and specialized offerings would offer pre-assembled sets of legos. Specialized IoT Platforms That’s the theory, at least. In reality, it doesn’t work like that. First, the CSPs keep changing the legos. More on that in a minute. Second, specialized IoT platforms are not sufficiently tailored to verticals to offer many advantages. They are too general. Often, they are developed around specific needs for one or two large clients and then marketed as platforms when actually they are simply applications built with typical CSP stacks that can be extended through development efforts for your project. Basically, they just code your project for you using the similar ideas and architectural components they used to develop the initial codeset. It has to be like this right now. You will see why in a minute. CSPs Are Disrupting Specialized Platforms CSPs control the IoT value chain and are disrupting the companies built on top of them. For example, at re:invent in November 2018, Amazon announced a new called . Time series databases handle loading and reading IoT data better than generic databases. Before TimeStream, if you wanted a time series database on AWS, it would have been necessary to run a third-party product, such as , on EC2 (Linux) in AWS and manage it yourself. time series database TimeStream Prometheus (TimeStream is only currently available in early release; Jan 2018) In 2018, I spoke with more than 30 companies who had built their specialized IoT platform on AWS. Most of these companies use MongoDB, DynamoDB (a fully managed AWS NoSQL database), or (mostly Postgres, MySQL, or Oracle). Some of the people I spoke with, even technical folks, had never heard of a time series database. Others complained that AWS did not offer one and that was too much of a black box to develop around. Either way, most vendors ended up writing complicated logic in the code to compensate for the lack of a time series database. AWS RDS AWS IoT Analytics The TimeStream announcement immediately obviated large swaths of these IoT platform architectures and, at the same time, made it easier for new platform entrants to enter the market. This is what’s known as cloud service providers moving up the stack. It is highly disruptive to companies built on top of CSPs and their customers. It is something you should be aware of when you are selecting your IoT Platform. The CSPs will continue to encroach on specialized platforms. IoT Platforms As Partners, Not Assets Some executives I have worked with intentionally treat third-party software as a black box and ignore the components that comprise it. The software is treated as a financial asset, such as a truck or a warehouse, that has a cost, utility, depreciation or operational expense, and can be readily replaced with a quantifiable amount of money, time and internal resources. In my experience, this approach can work well for commoditized software solutions, such as HR, sales, and accounting systems, but it is not the best way to approach IoT platforms right now. Emerging technologies, such as IoT platforms, should be treated more like strategic partnerships than assets or commodities because time and expense predictions for technology projects, in general, . (I wrote about this .) For emerging technology projects, they are worse than abysmal. If you can’t quantify expenses accurately, then it doesn’t make sense to treat third-party software as an asset. The salvage value is usually negative anyway. are abysmal in a previous post As CSPs continue to move up the stack, dependent platforms will be forced into a smaller and smaller technical arena. At the same time, it will become easier to implement IoT solutions on CSP platforms. This means the value of a specialized IoT platform, if it exists at all, will be in vertical expertise. Fostering this relationship can help create a complementary asset that helps protect and grow your long-term IoT initiatives. The end. There will be a second article. See . here Want to chat more / have an interesting proposal? Contact me at daniel@redchipventures.com

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