Ababhali: Neereja Sundaresan Theodore J. Yoder Youngseok Kim Muyuan Li Edward H. Chen Grace Harper Ted Thorbeck Andrew W. Cross Antonio D. Córcoles Maika Takita Isishwankathelo I-Quantum error correction inika indlela ethembisayo yokwenza ii-computations ze-quantum eziphakamileyo. Nangona ukwenziwa ngokupheleleyo kwe-algorithms egqityiweyo kusasele kungazaliseki, uphuculo olutsha ku-control electronics kunye ne-quantum hardware lunika amandla imiboniso ephucukileyo yokusebenza okudingekayo kulungiso lwempazamo. Apha, senza i-quantum error correction kwi-superconducting qubits ezidibene kwilattice ye-heavy-hexagon. Sikhona ukufaka i-logical qubit ngomgama ombuso ombuso ombuso wokuthathu kwaye senze imijikelo emininzi ye-syndrome measurement ethembekileyo evumela ukulungiswa kwempazamo nayiphi na ingxaki enye kwi-circuitry. Sisebenzisa impendulo yexesha lokwenyani, sibuyisela i-syndrome kunye ne-flag qubits ngokunyanisekisayo emva komjikelo ngamnye we-syndrome extraction. Sibika i-decoder-dependent logical error, ngempazamo ephakathi ye-logical per syndrome measurement kwi-Z(X)-basis ye-~0.040 (~0.088) kunye ne-~0.037 (~0.087) kwi-matching kunye ne-maximum likelihood decoders, ngokulandelanayo, kwidatha ye-leakage post-selected. Intshayelelo Iziphumo ze-quantum computations zingaba neempazamo, ngokwezendlalelo, ngenxa yengxolo kwi-hardware. Ukuphelisa iimpazamo ezivelayo, ii-quantum error correction (QEC) codes zingasetyenziselwa ukufaka ulwazi lwe-quantum kwi-degrees of freedom ezikhuselekileyo, ezifakwe kwi-logical, kwaye ke ngokulungisa iimpazamo ngokukhawuleza kunokuba ziqokelele zenze ii-computations ezithembekileyo (FT). Ukugqitywa okupheleleyo kwe-QEC kuya kufuna cishe: ukulungiswa kwe-logical states; ukufezekiswa kweseti epheleleyo ye-logical gates, enokudinga ukulungiswa kwe-magic states; imilinganiselo ephindaphindayo ye-syndromes; kunye nokudluliselwa kwe-syndromes zokulungisa iimpazamo. Ukuba iphumelele, iimpazamo eziphumelayo ze-logical kufuneka zibe ngaphantsi kweempazamo zomzimba ezifihliweyo, kwaye zinciphe ngomgama owandayo wekhodi wehlile ukuya kwiingxaki ezingabalulekanga. Ukukhetha i-QEC code kufuna ukuqwalaselwa kwe-hardware ezantsi kunye neempawu zayo zengxolo. Kwi-heavy-hexagon lattice , ye-qubits, ii-subsystem QEC codes ziyathandeka kuba zilungele ii-qubits ezineezixhobo ezincitshisiweyo. Ezinye ii-codes zibonise ithemba ngenxa yomda wabo ophakamileyo we-FT okanye inani elikhulu le-transversal logical gates . Nangona indawo yazo kunye ne-overhead yexesha zingabonisa umqobo omkhulu kwi-scalability, kukho iindlela ezikhuthazayo zokunciphisa izixhobo ezibiza kakhulu ngokusebenzisa uhlobo oluthile lokuphuculwa kwempazamo . 1 2 3 4 5 6 Kwinkqubo yokudluliselwa, ukulungiswa okuphumeleleyo kuxhomekeke kungekuphela kubuchule be-quantum hardware, kodwa nakwintsebenzo ye-control electronics esetyenziselwa ukufumana kunye nokucubungula ulwazi lweekhontrakthi olufunyenweyo kwimilinganiselo ye-syndrome. Kwimeko yethu, ukulungiswa kwe-syndrome kunye ne-flag qubits ngokusebenzisa impendulo yexesha lokwenyani phakathi kwemijikelo yomlinganiselo kunganceda ukunciphisa iimpazamo. Kwinqanaba lokudluliselwa, ngelixa ezinye iiprothokholi zikhona zokwenza i-QEC asynchronously ngaphakathi kommiselo we-FT , , izinga apho i-syndrome errors ifunyenwe khona kufuneka ihambelane neengxaki zayo zokucubungula iikhontrakthi ukunqanda ukwanda kwedatha ye-syndrome. Kwakhona, ezinye iiprothokholi, njengokusebenzisa i-magic state kwi-logical -gate , zifuna ukusetyenziswa kwempendulo yexesha lokwenyani. 7 8 T 9 Ke ngoko, umbono wexesha elide we-QEC awufani nenjongo enye enkulu kodwa kufanele ubonelele ngokuqhubeka kweemisebenzi edibene kakhulu. Indlela yovavanyo kuphuhliso lwesi sithekhnoloji iya kubandakanya imboniso yale misebenzi ngokwahlukileyo kuqala kunye nokudibanisa kwawo ngokuthe ngcembe kamva, ngelixa uphucula rhoqo iimfuno zawo. Ezinye zolu phuculo zibonakala kwizinto ezininzi ezintsha kwiinkqubo ze-quantum kwiindidi ezahlukeneyo zeenqanaba, ezibonise okanye zazisondeza kwiinkalo ezininzi zeemfuno ze-FT quantum computing. Ngokukodwa, ukulungiswa kwe-FT logical state kubonisiwe kwi-ions , i-nuclear spins kwi-diamond kunye nee-superconducting qubits . Imijikelo ephindaphindayo ye-syndrome extraction ibonisiwe kwi-superconducting qubits kwiikhowudi ezincinci zokufumanisa impazamo , , kubandakanya ukulungiswa kwempazamo ngokuyinxenye kunye neseti epheleleyo (nangona ingengayo i-FT) ye-single-qubit gates . Imboniso ye-FT yeseti epheleleyo ye-gate kwi-logical qubits ezimbini ibikwe kutshanje kwi-ions . Kwithala leempazamo, bekukho izinto ezintsha zamva nje zekhowudi yomhlaba enemigama emithathu kwi-superconducting qubits kunye nokudluliselwa kunye ne-post-selection , kunye nokusetyenziswa kwe-FT ye-dynamically protected quantum memory kusetyenziswa i-color code kunye ne-FT state preparation, operation, kunye nomlinganiselo, kubandakanya i-stabilizers yayo, ye-logical state kwi-Bacon-Shor code kwi-ions , . 10 11 12 13 14 15 16 17 18 19 20 20 21 Apha sidibanisa amandla empendulo yexesha lokwenyani kwi-superconducting qubit system kunye ne-maximum likelihood decoding protocol engazange iphonongwe ngokuvavanywa ukuphucula ukusinda kwe-logical states. Sibonisa ezi zixhobo njengenxalenye yomsebenzi we-FT we-subsystem code , i-heavy-hexagon code , kwi-superconducting quantum processor. Kubalulekile ukwenza usetyenziso lwethu lwekhodi lufakamele iimpazamo zii-flag qubits ezithi, xa zifunyaniswa zingekho zero, zitsalele umdla umdlulisi kwiimpazamo zesekethe. Ngokubuyisela ngokunyaniseka i-flag kunye ne-syndrome qubits emva komjikelo ngamnye womlinganiselo we-syndrome, sikhusela inkqubo yethu kwiimpazamo ezivela kwi-noise asymmetry eyenzeka nge-energy relaxation. Siphinde sisebenzise izicwangciso zokudluliselwa ezichazwe kutshanje kwaye sandise izimvo zokudluliselwa ukubandakanya iingcamango zokuphambana kwe-maximum , , . 22 1 15 4 23 24 Iziphumo I-heavy-hexagon code kunye nemijikelo emininzi I-heavy-hexagon code esiyiqwalaselayo yikhowudi ye- = 9 qubit ehlanganisa i- = 1 logical qubit ngomgama = 3 . Ii- kunye ne- gauge (bona uMzekiso. a) kunye namaqela e-stabilizer enziwa yi n k d 1 Z X 1 Iiqela ze-stabilizer ziiziko leziqwengezizo zeqela le-gauge le-respective . Oku kuthetha ukuba ii-stabilizers, njengeemveliso zabasebenzi be-gauge, zingafunyanwa kumilinganiselo yabasebenzi be-gauge kuphela. Ii-operators ze-logical zingakhethwa ukuba zi- = 1 2 3 kunye ne- = 1 3 7. XL X X X ZL Z Z Z Ii-operators ze- (blue) kunye ne- (red) gauge (ii-eqs. ( ) kunye ( )) ezifakwe kwi-qubits ezingama-23 ezifunekayo kunye nekhowudi ye-heavy-hexagon enemigama emithathu. Ii-qubits zekhowudi ( 1 − 9) zibonisiwe ngomthubi, ii-syndrome qubits ( 17, 19, 20, 22) ezisetyenziselwa ii- stabilizers ngoluhlaza okwesibhakabhaka, kunye nee-flag qubits kunye nee-syndromes ezisetyenziselwa ii- stabilizers ngomhlophe. Umyalelo kunye nenkqubo apho ii-CX gates zisetyenziswayo kwiindawo ezithile (0 ukuya kwezi-4) ziboniswa ziintolo ezinenombolo. Umzobo wesekethe yomjikelo omnye we-syndrome measurement, kubandakanya ii- kunye ne- stabilizers. Umzobo wesekethe ubonisa ukuhlanganiswa okuvunyiweyo kokuqhutywa kwe-gate: ezo zingaphakathi kwemida emiselweyo zii-barriers zokucwangcisa (iintambo ezintshona ezimele nkqo). Njengoko ubude besango ngalinye le-qubit ezimbini buhluka, ukucwangcisa kwe-gate yokugqibela kunqunyulwa ngomnqamlezo wokugqibela ongocwangciso wedatha ongagqibekanga; emva koko, i-dynamical decoupling yongezwa kwi-data qubits apho ixesha livumela khona. Imilinganiselo kunye ne-reset operations zihlukile kwezinye izenzo ze-gate ngeebarriers ukuvumela i-dynamical decoupling efanayo ukuba yongezwe kwi-data qubits engasebenzi. Ii-graphs zokudluliselwa zemijikelo emithathu ye- ( ) kunye ne- ( ) stabilizer measurements kunye ne-circuit-level noise ivumela ukulungiswa kwe- kunye ne- errors, ngokulandelanayo. Ii-nodes eziluhlaza okwesibhakabhaka kunye nemibala ebomvu kwiigrafts zichaza i-syndromes ezahlukileyo, ngelixa ii-nodes ezimnyama ziyindawo yediliya. Iintolo zibonisa iindlela ezahlukeneyo iimpazamo ezinokwenzeka kwi-circuit njengoko kuchaziwe kwisicatshulwa. Ii-nodes zigcinwe ngohlobo lomlinganiselo we-stabilizer ( okanye ), kunye ne-subscript ebonisa i-stabilizer, kunye ne-superscript ebonisa umjikelo. Iintolo ezimnyama, ezivela kwi-Pauli errors kwi-code qubits (kwaye ke ngoko ziziqu-2 kuphela), zixhuma ii-graphs ezimbini kwi- ( ) kunye ne- ( ), kodwa azisetyenziswa kwi-matching decoder. Iii-hyperedges eziziqu-4, ezingasetyenziswa yimatch, kodwa zisetyenziswa kwi-maximum likelihood decoder. Imibala yeyokucaca kuphela. Ukuguqulela nganye ngexesha enye imijikelo kwenza i-hyperedge evumelekileyo (kunye nokwahluka okuthile kwimida yexesha). Kwakhona azibonisi naziphi na ii-hyperedges eziziqu-3. a Z X 1 2 Q Q Q Q Q Q Z X b X Z c Z d X X Z Z X e Y c d f Apha sigxininisa kwi-FT circuit ethile, uninzi lwezicwangciso zethu zingasetyenziswa ngokubanzi kunye nee-codes ezahlukeneyo kunye nee-circuits. Ii-sub-circuits ezimbini, eziboniswe kuMzekiso. b, zakhiwe ukulinganisa ii-operators ze- - kunye ne- -gauge. Umzobo wokulinganisa we- -gauge ukwenza ulwazi oluyimfuno ngokulinganisa ii-flag qubits. 1 X Z Z Silungisa ii-code states kwisimo se-logical () ngokulungisa kuqala ii-qubits ezilithoba kwisimo se- () kwaye silinge i- -gauge ( -gauge). Emva koko senze imijikelo ye-syndrome measurement , apho umjikelo ubandakanya umlinganiselo we- -gauge okulandelwa ngumlinganiselo we- -gauge (ngokulandelanayo, i- -gauge ilandelwe yi- -gauge). Ekugqibeleni, sifunda zonke ii-qubits ezilithoba kwisisekelo se- ( ). Senza uvavanyo olufanayo kwi-logical states yokuqala kunye kwanje, ngokulungisa nje ii-qubits ezilithoba kwi- kunye ne- endaweni. X Z r Z X X Z Z X Izi-algorithms zokudluliselwa Kwindawo ye-FT quantum computing, umdlulisi ngumnqamlezo othatha njengomgangatho imilinganiselo ye-syndrome ukusuka kwikhowudi yokulungisa impazamo kwaye uphume isilungiso kwi-qubits okanye idatha yomlinganiselo. Kwicandelo elingezantsi sichaza ii-algorithms ezimbini zokudluliselwa: ukudluliselwa kwe-matching egqibeleleyo kunye nokudluliselwa kwe-maximum likelihood. I-hypergraph yokudluliselwa yinkcazo efutshane yolwazi oluqokelelwe yi-FT circuit kwaye lwenziwe lufumaneke komdlulisi womsebenzi. Iquka iseti yee-vertices, okanye imisitho enobunxaxhi , , kunye neseti ye-hyperedges , ezifaka ubudlelwane phakathi kwemisitho ebangelwa yimiphumo kwi-circuit. Umzekelo. c–f ibonisa iindawo ze-hypergraph yokudluliselwa kuvavanyo lwethu. 15 15 V E 1 Ukuhlanganisa i-hypergraph yokudluliselwa yee-circuits ze-stabilizer kunye ne-Pauli noise kungenziwa kusetyenziswa ii-simulations ze-Gottesman-Knill zemveli okanye iindlela ezifanayo ze-Pauli tracing . Okokuqala, imisitho enobunxaxhi iyadalwa kulo lonke umlinganiselo onokuthembela kwimpazamo, ongayi kunika isiphumo. Umlinganiselo onokuthembela nguwuphi na umlinganiselo onokuthembela ophume kuyo ∈ {0, 1} ungachazwa ngokongeza i-modulo ezimbini imiphumo yomlinganiselo ukusuka kwiseti yemilinganiselo yangaphambili. Oko kukuthi, kwi-circuit engenawo impazamo, kunye neseti ingafunyanwa ngokudluliselwa kwe-circuit. Misela ixabiso lemsitho enobunxaxhi ku − (mod2), elingalinganiyo (libizwa ngokuba yinto engeyonyani) xa kungekho mpazamo. Ngoko ke, ukubona imisitho enobunxaxhi engalinganiyo (ekwabizwa ngokuba yinto engabonakaliyo) ibonisa ukuba i-circuit iye yafumana impazamo enye okanye ngaphezulu. Kwi-circuits zethu, imisitho enobunxaxhi yimilinganiselo ye-flag qubit okanye umahluko weemilinganiselo ezilandelanayo zazo zonke i-stabilizer (ekwabizwa ngokuba yii-syndromes ezahlukeneyo). 25 26 M m , m FM Emva koko, ii-hyperedges ziyongezwa ngokucinga ngeempazamo zesekethe. Imifanekiso yethu iquka ubuninzi bempazamo kwiingqalelo ezithile zesekethe pC Apha sikhetha phakathi kokusebenza kobuchaphaphayo id kwi-qubits ngexesha apho ii-qubits zodidi zenza ii-unitary gates, ukusuka ekusebenzeni kobuchaphaphayo idm kwi-qubits xa ii-qubits zodidi zenza imilinganiselo kunye nokubuyisela. Sibuyisela ii-qubits emva kokuba zilinyelwe, ngelixa silungisa ii-qubits ezingekasetyenziswa kuvavanyo okwangoku. Okokugqibela i-cx yiyona nto ilawulwa-kungabikho, i-h yiyona nto i-Hadamard, kwaye i-x, y, z zii-Pauli gates. (bona iindlela “IBM_Peekskill kunye neenkcukacha zovavanyo” ukuze ufumane iinkcukacha ezininzi). Amaxabiso amanani e- afakwe kwiindlela “IBM_Peekskill kunye neenkcukacha zovavanyo”. pC Imodeli yempazamo yethu yiyona ndlela yokudlulisela i-circuit depolarizing noise. Kwiimpazamo zokulungisa kunye nokubuyisela, i-Pauli ibandakanyeka kunye nobumnini obuhambelanayo kwaye emva kokulungiswa kwestatshi okuchanekileyo. Kwiimpazamo zokulinganisa, i-Pauli ibandakanyeka kunye nobumnini ngaphambi kokulinganiswa okuchanekileyo. Isango lobuchaphaphayo elinye i-qubit (isango le-qubit ezimbini) lifumana ngobumnini elinye lee-Pauli errors ezintathu (ezilishumi elinamihlanu) ezingezizo ubuchaphaphayo ezilandelanayo nesango elichanekileyo. Kukho ithemba elilinganayo lokuvela kwazo zonke ii-Pauli errors ezintathu (ezilishumi elinamihlanu). X pinit preset X C pC Xa impazamo enye yenzeka kwi-circuit, ibangela ukuba iseti ethile yeemisitho enobunxaxhi ingabi yinto engeyonyani. Esi siganeko semisitho enobunxaxhi siba yi-hyperedge. Isiganeko se-hyperedges zonke yi- . Iimpazamo ezimbini ezahlukeneyo zingavelisa i-hyperedge efanayo, ngoko ke i-hyperedge nganye ingabonwa njengokumela iseti yeempazamo, nganye yazo ngokwehlukileyo ibangela imisitho kwi-hyperedge ingabi yinto engeyonyani. Ixabiso elihambelanayo kunye ne-hyperedge, kwindawo yokuqala, yiyo idatshana lezibambiso zeempazamo kwiseti. E Impazamo ingakhokelela kwimpazamo ethi, xa idluliselwe kwisiphelo sesekethe, i-anti-commutes kunye ne-operator enye okanye ngaphezulu yeekhowudi, ifuna isilungiso se-logical. Siyakholelwa jikelele ukuba ikhowudi inee- logical qubits kunye nesiseko see-operators ze-logical 2 , kodwa qaphela = 1 yee-heavy-hexagon code esetyenziswayo kuvavanyo. Singagcina umkhondo wokuba yeyiphi ii-operators ze-logical ezithatha i-anti-commute kunye nempazamo kusetyenziswa i-vector ukusuka ku . Ngoko ke, i-hyperedge nganye ikwabhalwe kunye nenye yezi vector , ebizwa ngokuba yi-logical label. Qaphela ukuba ukuba ikhowudi inomgama ombuso ubuncinci, i-hyperedge nganye inomsebenzi oyimfihlo omnye. k k k h Ekugqibeleni, siyaphawula ukuba umdlulisi womsebenzi angakhetha ukwenza lula i-hypergraph yokudluliselwa ngeendlela ezahlukeneyo. Indlela enye esiyisebenzisayo rhoqo apha yinkqubo yokususa i-flagging. Imilinganiselo ye-flag ukusuka kwi-qubits 16, 18, 21, 23 iyavalwa nje ngaphandle kokufakwa kwezilungiso. Ukuba i-flag 11 ayinayo into kwaye i-12 ingeyonyani, faka ku-2. Ukuba i-12 ayinayo into kwaye i-11 yinto engeyonyani, faka kwi-qubit 6. Ukuba i-flag 13 ayinayo into kwaye i-14 yinto engeyonyani, faka kwi-qubit 4. Ukuba i-14 ayinayo into kwaye i-13 yinto engeyonyani, faka kwi-qubit 8. Bona i-ref. ngeenkcukacha malunga nokuba kutheni oku kunganele ukuba kufakamele iimpazamo. Oku kuthetha ukuba endaweni yokubandakanya imisitho enobunxaxhi evela kwimilinganiselo ye-flag qubit, siphatha kwangaphambili idatha ngokusebenzisa ulwazi lwe-flag ukufaka izilungiso ze-Pauli ezibonakalayo kwaye uhlengahlengise imisitho enobunxaxhi elandelayo ngokuhambelanayo. Ii-Hyperedges ze-hypergraph egugulelweyo zingafumaneka ngokudluliselwa kwe-stabilizer okubandakanya izilungiso ze- . Vumela ibonise inani lemijikelezo. Emva kokususa i-flagging, ubungakanani beseti ye- (respa. -basis) uvavanyo ngu-∣ ∣ = 6 + 2 (respa. 6 + 4), ngenxa yokulinganisa ii-stabilizers ezintandathu kumjikelo ngamnye kwaye sinezimbini (respa. ezine) ii-syndrome stabilizers zokuqala emva kokulungiswa kwesitatshi. Ubungakanani be- buyefana Z Z Z Z 15 Z Z r V Z X V r r E ∣E
