Top 4 HDL Simulators for Beginners

When learning to program FPGAs or ASICs using hardware description languages, such as Verilog or VHDL, being able to simulate code is an important part of the learning process.

In fact, being able to run simulations is crucial in understanding how our code behaves. For beginners, running simulations can also be helpful in demonstrating how new syntax or concepts work in the HDL they are learning.

However, there are a number of different simulators on the market, each with its own strengths and weaknesses. As a result of this, it can be difficult to know which is the best tool to use.

This choice is further complicated by the fact that there is not a readily available one size fits all solution unless you are willing to pay for a commercial product such as QuestaSim.

In this article, we look at four of the most popular HDL simulators on the market. This includes a summary of the strengths and weaknesses of each tool to make it simpler for a beginner to select the best HDL simulation tool.

Icarus Verilog

Icarus Verilog is a fully open-source compiler that includes both a Verilog synthesizer and simulator. It is one of the most popular open-source Verilog simulators. It is even one of the simulators which can be used on the popular EDA playground website.

Icarus Verilog can be used on Windows, macOS, or Linux-based operating systems. It offers full support for the Verilog-2005 standard as well as limited support for SystemVerilog.

There are several reasons why Icarus Verilog is a good choice for beginners. As it is an open-source tool, Icarus Verilog can be used for free. However, there is still a community of developers which maintain Icarus Verilog and update it with new features.

Another thing that makes Icarus an attractive tool for beginners is its ease of use. In order to run a basic simulation, only a few simple commands are required.

However, there are also some disadvantages to Icarus Verilog.

One of the biggest drawbacks is that Icarus Verilog doesn’t display waveforms by default. This is typically a useful feature as it makes it easier for us to debug our HDL-based designs.

However, it is possible to export waveforms into the open-source GTKWave software to look at the waveforms.

In addition to this, Icarus Verilog only offers full support for Verilog. That means it is not possible to run simulations that use either VHDL or SystemVerilog with this tool.

TL;DR

GHDL

GHDL is a fully open-source VHDL compiler and simulator which is nearly 20 years old. A community of developers on Github maintains the GHDL code base and regularly releases new updates.

We can use GHDL on Windows, macOS, or Linux-based operating systems. GHDL currently offers full support for the VHDL-87, 93, and 2002 standards. In addition to this, many of the most valuable features of VHDL-2008 are also supported.

GHDL is the most popular open-source VHDL simulator. As a result of this popularity, it is also one of the simulators featured on the EDA playground.

One reason for this popularity is that it offers support for many features of the VHDL-2008 standard. This is directly comparable to many commercially available simulators, most of which still offer only limited VHDL-2008 support.

Another feature that makes GHDL attractive for beginners is the ease of use. It is possible to simulate VHDL-based designs using only two commands.

For more advanced users, GHDL also offers easy support for simulation libraries such as OSVVM and UVVM.

However, there are a few drawbacks to using GHDL.

As with Icarus Verilog, there is no way to display waveforms from our simulations in GHDL. This means that we have to export waveforms into the free GTKWave software if we want to view them.

In addition to this, we can only use GHDL to simulate VHDL-based designs. This means that we would need to find another tool if we wanted multi-language support.

TL;DR

Vivado

Vivado is a software tool from Xilinx which can be used to design, simulate and build FPGAs. Unlike the other tools we have discussed so far, Vivado is commercially developed and maintained. As a result, Vivado is regularly updated with new features and bug fixes.

There are several different licensing options for Vivado, depending on which families of FPGA are being targeted. However, there is a free version for beginners that can be used for basic designs and simulations.

We can use Vivado on Windows and Linux-based operating systems, but currently, there is no support for macOS.

We can use Vivado to simulate designs using any of SystemVerilog, VHDL, or Verilog. This is a clear advantage over GHDL or Icarus, which only offer support for one language.

Although there is a learning curve when it comes to using Vivado to build FPGAs, it is relatively simple to use for simple simulations. It also offers a graphical user interface, unlike the open-source tools we have discussed so far.

Another benefit of using Vivado for simulations is that it natively supports the viewing of waveforms. This is especially useful for beginners as it makes it easy to quickly visualize what is happening in a simulation.

However, there are also some disadvantages to using Vivado as an HDL simulator.

One of the drawbacks of Vivado is that it typically requires a large install, requiring more significantly more than 10GB to install. The reason for this is that it is a suite of tools designed to simulate FPGAs and build bitstreams that can be used to program the physical device.

Another drawback of Vivado is that it doesn’t feature full support for VHDL-2008. However, this support is being improved with each new release of the software.

It can also be difficult for more advanced users to use third-party simulation libraries such as UVM and OSVVM with Vivado.

TL;DR

ModelSim

Modelsim is a commercially produced simulation tool from Siemens. It is a stripped-down version of the Questa simulator, which is one of the most popular industrially used HDL simulators.

Although Modelsim is a paid tool, it is possible to get free versions as a part of the Intel or Microchip FPGA toolchains.

Modelsim can be used on Linux or Windows-based operating systems but not on macOS.

Unlike the open-source tools, we can use Modelsim to simulate designs that use a mixture of SystemVerilog, VHDL, or Verilog.

In addition to this, Modelsim features a GUI, which makes it possible to view waveforms without having to use an additional software tool. As we have already discussed, this is especially useful for beginners as it makes it easy to visualize what is happening in a simulation.

However, there are some disadvantages to using Modelsim for HDL simulations.

In comparison to the other tools we have discussed, Modelsim is the most difficult to use. In order to run simulations effectively, it is necessary to write scripts using tcl. Although it is not necessary to master tcl to write these scripts, some basic understanding is at least required.

One of the reasons that Questa and Modelsim are commercially popular tools is that they offer fast simulation times. However, the performance of the free version is deliberately restricted, meaning that it can be slow to run simulations.

Although Modelsim offers support for SystemVerilog, several of the key features of the language are not supported. This includes most of the verification-related features, such as classes and functional coverage.

TL;DR

For those new to programming using HDLs such as VHDL and Verilog, it is important to run simulations to better understand how the language works. I hope this article will help them choose the right simulator.