Bidirectional Microwave-optical Transduction Based on Integration: Appendix B: Fabrication

Table of Links

• Introduction

  
  

• Results

• A. Physics and design

• B. Device characterization

• C. Bidirectional microwave-optical transduction

• D. Pulsed transduction

  
  

• Discussion

• Acknowledgments

• Appendix A: Theory

• Appendix B: Fabrication process flow

• Appendix C: Optical characterization

• Appendix D: Characterization of acoustic resonances

• Appendix E: Characterization of bidirectional transduction

• Appendix F: Optimization of optical extraction efficiency

Appendix B: Fabrication process flow

The piezoelectric actuators are monolithically integrated on Si3N4 waveguides, fabricated using the photonic Damascene process [7, 8]. The 850-nm-thick Si3N4 film is deposited using low-pressure chemical vapor deposition into the Damascene preform, with 2.8 µm thermal oxide below the waveguides. After annealing to drive hydrogen impurities out of the Si3N4 layer, 2.1-µm-thick TEOS oxide and 1.0-µm-thick low-temperature oxide top claddings are deposited and subsequently annealed. The metallic and piezoelectric films—95 nm of Mo, 1.0 µm of AlN and another 95 nm of Mo—are sputtered through foundry services provided by Plasma-Therm [9]. They are then patterned using deep reactive ion etching (DRIE) to form the actuators, ground planes and integrated heaters. We employ the same BandAid process as in Ref. [10] to localize the electrodes atop the suspended cladding. In particular, when connecting the Al feedline to the top electrode by a lift-off process, the bottom electrode is etched back using XeF2 to avoid shortcircuiting the electrodes. The process to suspend the cladding in the vicinity of the actuator is combined with the chip singulation steps of the Damascene process. First, a hole is opened in the middle of the donut-shaped actuator. The chip facets are simultaneously defined where trenches in the SiO2 are etched by C4F8 DRIE between neighboring chips. A second photolithography is performed to protect the facets while leaving the etched holes exposed for further processing, resulting in narrower trenches between chips. The Si substrate is then isotropically etched with SF6 until the SiO2 cladding below the actuator is suspended [11]. Following cladding suspension, the Si substrate is etched anisotropically until the desired chip thickness of 250 µm is reached. A final isotropic Si etch removes the parts of the substrate protruding from the SiO2 facet, providing proper access to the bus waveguide nanotapers with lensed fibers, or even using the butt-coupling scheme. To facilitate this last step, we employ ion-beam etching at a 20◦ tilt angle to remove the passivation layer formed on the hole sidewalls during the Si DRIE. The chips are ultimately released by grinding the back side of the wafer. This convoluted process ensures that all the actuators on the wafer are fully suspended, while the chip facets do not become exceedingly fragile from the undercut.