logicleak

I’m an RTL Design Engineer with a Master’s degree in Electrical Engineering, specializing in VLSI and semiconductor systems. I bring end-to-end knowledge of the semiconductor lifecycle—from design and verification to manufacturing, testing, and packaging. My core expertise lies in RTL design, low-power architectures, and SoC development, with hands-on experience in industry-standard tools such as Synopsys VCS, VC CDC, VC Lint, and low-power verification flows. I’ve worked on complex digital systems involving fuse controllers, clock domain crossing (CDC), and indirect register addressing, focusing on building reliable and scalable hardware. Beyond design, I have a strong understanding of the broader chip development pipeline—including front-end design, back-end implementation, fabrication processes, wafer sort, packaging, and final testing. I’m particularly interested in how emerging technologies like AI can enhance defect detection, yield optimization, and overall semiconductor manuf